DK-DEV-5AGXB3N/ES【PDF 26/39 页】ARRIA V DEVELOPMENT KIT

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Transceiver Channels

Figure 10: Device Chip Overview for Arria V GZ Devices

I/O, LVDS, and Memory Interface

I/O, LVDS, and Memory Interface

Figure 11: Device Chip Overview for Arria V SX and ST Devices

FPGA I/O, LVDS, and Memory Interface

HPS I/O

FPGA Hard Memory Controller

HPS

Hard

Transceiver

PCS

PMA

Hard

Transceiver

PCS

PMA

Transceiver

Hard

PMA

PCS

Transceiver

Individual Channels

Core Logic Fabric

and MLABs

M20K Internal

Memory Blocks

Variable-Precision

DSP Blocks

Hard

Transceiver

PCS

PMA

Hard

Transceiver

PCS

PMA

Transceiver

Hard

PMA

PCS

Transceiver

Individual Channels

Core Logic Fabric

and MLABs

M10K Internal

Memory Blocks

AV-51001

2013.12.26

Altera Corporation

FPGA Hard Memory Controller

FPGA I/O, LVDS, and Memory Interface

Variable-Precision

DSP Blocks

Arria V Device Overview

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